封装信息
| Pkg. Type: | TQFP |
| Pkg. Code: | PRG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 1.4 |
| Pitch (mm): | 0.8 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
产品属性
| Pkg. Type | TQFP |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| C-C Jitter Max P-P (ps) | 100 |
| Core Voltage (V) | 3.3V, 2.5V |
| Divider Value | 2, 4, 6 |
| Feedback Input | Yes |
| Input Freq (MHz) | 16.67 - 100 |
| Input Type | LVCMOS, LVTTL |
| Inputs (#) | 1 |
| Length (mm) | 7 |
| MOQ | 125 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 16.67 - 200 |
| Output Signaling | LVCMOS, LVTTL |
| Output Skew (ps) | 100 |
| Output Type | LVCMOS, LVTTL |
| Output Voltage (V) | 3.3V, 2.5V |
| Outputs (#) | 11 |
| Package Area (mm²) | 49 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 75 |
| Phase Jitter Typ RMS (ps) | 20 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 250 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1.4 |
| Width (mm) | 7 |
| 已发布 | No |
有关 5V9352 的资源
描述
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver targeted for high performance clock tree applications. It uses a PLL to precisely align, in both frequency and phase. The 5V9352 operates at 2.5V and 3.3V. FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The 5V9352 features three banks of individually configurable outputs. The banks are configured with five, four, and two outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. The output frequency relationship is controlled by the fSEL frequency control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL compatible inputs Unlike many products containing PLLs, the 5V9352 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the 5V9352 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at REFCLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by setting the PLL_EN to high. The 5V9352 is available in Industrial temperature range (-40°C to +85°C).