封装信息
| Pkg. Type: | PLCC |
| Pkg. Code: | PLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 13.97 x 11.43 x 2.79 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
产品属性
| Pkg. Type | PLCC |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| C-C Jitter Max P-P (ps) | 200 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | 3.3 |
| Feedback Input | Yes |
| Function | Clock Generator |
| Input Freq (MHz) | 3.75 - 85 |
| Input Type | LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 13.97 |
| MOQ | 64 |
| Moisture Sensitivity Level (MSL) | 3 |
| Operating Freq | 85 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 3.75 - 85 |
| Output Signaling | LVCMOS |
| Output Skew (ps) | 250 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 8 |
| Package Area (mm²) | 159.7 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 13.97 x 11.43 x 2.79 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 32 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 2.79 |
| Width (mm) | 11.43 |
| 已发布 | No |
有关 5V991A 的资源
描述
The 5V991A is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. Akey feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5V991A has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/PE is held low, all the outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.