封装信息
| Lead Count (#) | 64 |
| Pkg. Type | TQFP |
| Pkg. Code | PPG64 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.4 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
| Moisture Sensitivity Level (MSL) | 3 |
产品属性
| Pkg. Type | TQFP |
| Lead Count (#) | 64 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| Advanced Features | Programmable Clock, Reference Output |
| App Jitter Compliance | GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813, ITU-T G.783, Stratum 3, SMC, 4E, 4 Clocks |
| Core Voltage (V) | 3.3 |
| Input Freq (MHz) | 0.002 - 622.08 |
| Input Type | LVPECL, LVDS, LVCMOS |
| Inputs (#) | 8 |
| Length (mm) | 10 |
| MOQ | 160 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 0.000001 - 622.08 |
| Output Skew (ps) | 50 |
| Output Type | LVPECL, LVDS, LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 4 |
| Package Area (mm²) | 100.0 |
| Pb Free Category | e3 Sn |
| Phase Jitter Typ RMS (ps) | 4.300 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.4 |
| Prog. Clock | Yes |
| Prog. Interface | Serial, JTAG |
| Qty. per Carrier (#) | 160 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Temp. Range | 0 to 70°C |
| Thickness (mm) | 1.4 |
| Width (mm) | 10 |
有关 82V3352 的资源
描述
The 82V3352 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The T0 path supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.