跳转到主要内容
Clock Generator For Cavium Processors

封装信息

Lead Count (#) 48
Pkg. Code DXG48
Pitch (mm) 0.5
Pkg. Type PTQFP
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.0

环境和出口类别

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 48
Carrier Type Tray
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 0
Qty. per Carrier (#) 250
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to +85°C
Advanced Features Reference Output
App Jitter Compliance PCI/PCI-X
Core Voltage (V) 3.3
Feedback Input No
Input Freq (MHz) 25 - 25
Input Type Crystal, CML, LVCMOS, LVDS, LVPECL
Inputs (#) 2
Length (mm) 7
MOQ 250
Output Banks (#) 6
Output Freq Range (MHz) 25 - 25, 33.333 - 33.333, 50 - 50, 66.667 - 66.667, 80 - 80, 83.333 - 83.333, 100 - 100, 125 - 125, 133.333 - 133.333
Output Skew (ps) 25
Output Type LVCMOS, LVDS, LVPECL
Output Voltage (V) 2.5, 3.3
Outputs (#) 10
Package Area (mm²) 49.0
Period Jitter Max P-P (ps) 90.000
Phase Jitter Typ RMS (ps) 0.557
Pitch (mm) 0.5
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.0
Pkg. Type PTQFP
Prog. Clock No
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Tape & Reel No
Thickness (mm) 1
Width (mm) 7

描述

The 8430S803I is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the 8430S803I supports telecommunication, networking, and storage requirements.