概览
描述
The 8634-01 is a high performance 1-to-5 Differential-to- 3.3V LVPECL Zero Delay Buffer. The 8634-01 has two selectable clock inputs. The CLKx, nCLKx pair can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.
特性
- Five differential 3.3V LVPECL outputs
- Selectable differential clock inputs
- CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
- Output frequency range: 31.25MHz to 700MHz
- Input frequency range: 31.25MHz to 700MHz
- VCO range: 250MHz to 700MHz
- External feedback for "zero delay" clock regeneration
- Cycle-to-cycle jitter: 25ps (maximum)
- Output skew: 25ps (maximum)
- PLL reference zero delay: 50ps ± 100ps
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Lead-Free package available
- Industrial temperature information available upon request
产品对比
应用
设计和开发
模型
ECAD 模块
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模型
| 模型 - IBIS | ZIP 29 KB | |
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