封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CABGA |
| Pkg. Code: | BFG81 |
| Lead Count (#): | 81 |
| Pkg. Dimensions (mm): | 8.0 x 8.0 x 1.35 |
| Pitch (mm): | 0.8 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 81 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 360 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e1 SnAgCu |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | No |
| Additive Phase Jitter Typ RMS (fs) | 77 |
| Additive Phase Jitter Typ RMS (ps) | 0.077 |
| Adjustable Phase | Yes |
| Advanced Features | Holdover, Phase Delay, Input Switching, JESD204B, Programmable Clock |
| Channels (#) | 1 |
| Core Voltage (V) | 3.3V |
| DPLL Channels (#) | 0 |
| Feedback Divider Resolution (bits) | 15 |
| Fractional Output Dividers (#) | 0 |
| Frequency Plan | 2949.12 / Output_Divider, 2457.6 / Output_Divider, 2500 / Output_Divider |
| Input Freq (MHz) | 0.008 - 307.2 |
| Input Redundancy | Input Monitor, Auto-switch, Manual switch, Revertive and non-revertive switch, Holdover |
| Input Ref. Divider Resolution (bits) | 15 |
| Input Type | LVDS, LVPECL |
| Inputs (#) | 2 |
| JESD204B/C Compliant | No |
| Length (mm) | 8 |
| Loop Bandwidth Range (Hz) | 20 - 100 |
| MOQ | 360 |
| Noise Floor (dBc/Hz) | -161 |
| Output Banks (#) | 4 |
| Output Divider Resolution (bits) | 8 |
| Output Freq Range (MHz) | 15.36 - 2949.12 |
| Output Skew (ps) | 41 |
| Output Type | LVDS, LVPECL |
| Output Voltage (V) | 3.3V, 2.5V, 1.8V |
| Outputs (#) | 10 |
| PLL | Yes |
| Package Area (mm²) | 64 |
| Phase Jitter Typ RMS (fs) | 73 |
| Phase Jitter Typ RMS (ps) | 0.073 |
| Phase Noise Supports GSM | Yes |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 8.0 x 8.0 x 1.35 |
| Pkg. Type | CABGA |
| Ports (#) | 1 |
| Price (USD) | $17.41597 |
| Product Category | FemtoClock 2 |
| Prog. Clock | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Synthesis Mode | Integer |
| Tape & Reel | No |
| Thickness (mm) | 1.35 |
| Width (mm) | 8 |
| Xtal Freq (KHz) | 30720 - 250000 |
| 已发布 | No |
有关 8V19N470 的资源
描述
The 8V19N470 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, LTE-A radio board implementations.
A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency. This PLL has two VCO circuits at 2949.12MHz and 2400MHz – 2500MHz, respectively, for enhanced frequency flexibility.
The device generates the output clock signals from the selected VCO by frequency division. Four independent integer frequency dividers are available. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clockswitching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. The device is configured through an SPI interface and reports PLL lock and signal loss status in internal registers, PLL lock status is also reported via two lock detect outputs. Internal status bit changes can also be reported via the nINT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging and instrumentation/medical applications.
For information regarding evaluation boards and material, please contact your local sales representative.