封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CABGA |
| Pkg. Code: | BDG100 |
| Lead Count (#): | 100 |
| Pkg. Dimensions (mm): | 11.0 x 11.0 x 1.2 |
| Pitch (mm): | 1 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 100 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e1 SnAgCu |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | No |
| Additive Phase Jitter Typ RMS (fs) | 52 |
| Additive Phase Jitter Typ RMS (ps) | 0.052 |
| Adjustable Phase | Yes |
| Advanced Features | Holdover, Input Switching, JESD204B |
| Channels (#) | 1 |
| Core Voltage (V) | 1.8V |
| DPLL Channels (#) | 0 |
| Feedback Divider Resolution (bits) | 15 |
| Fractional Output Dividers (#) | 0 |
| Frequency Plan | 3932.16 / Output_Divider |
| Grade | 5G |
| Input Freq (MHz) | 0.00375 - 2000 |
| Input Redundancy | Input Monitor, Auto-switch, Manual input switch, Holdover |
| Input Ref. Divider Resolution (bits) | 15 |
| Input Type | LVDS, LVPECL |
| Inputs (#) | 4 |
| JESD204B/C Compliant | Yes |
| Length (mm) | 11 |
| Loop Bandwidth Range (Hz) | 20 - 100 |
| MOQ | 168 |
| Noise Floor (dBc/Hz) | -160 |
| Output Banks (#) | 8 |
| Output Divider Resolution (bits) | 7 |
| Output Freq Range (MHz) | 0.192 - 6000 |
| Output Skew (ps) | 100 |
| Output Type | LVDS, LVPECL |
| Output Voltage (V) | 1.8V, 3.3V |
| Outputs (#) | 18 |
| PLL | Yes |
| Package Area (mm²) | 64 |
| Phase Jitter Typ RMS (fs) | 74 |
| Phase Jitter Typ RMS (ps) | 0.074 |
| Phase Noise Supports GSM | Yes |
| Pitch (mm) | 1 |
| Pkg. Dimensions (mm) | 11.0 x 11.0 x 1.2 |
| Pkg. Type | CABGA |
| Ports (#) | 1 |
| Price (USD) | $22.24119 |
| Prog. Clock | Yes |
| Supply Voltage (V) | 3.3 - 3.3, 1.8 - 1.8 |
| Synthesis Mode | Integer |
| Tape & Reel | No |
| Thickness (mm) | 1.2 |
| Width (mm) | 11 |
| Xtal Freq (KHz) | 15000 - 500000 |
| 已发布 | No |
有关 8V19N880 的资源
描述
The 8V19N880 is a fully integrated FemtoClock® RF Sampling Clock Generator and Jitter Attenuator designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in 4G, 5G and including mmWave radio implementations. The device supports JESD204B (subclass 0 and 1) and JESD204C.
A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for the best possible phase noise characteristics. The second stage PLL locks on the first PLL output signal and synthesizes the target frequency. The second stage PLL can use the internal or an external high-frequency VCO.
The device generates the high-frequency clocks and the low-frequency synchronization signals (SYSREF) from the selected VCO. SYSREF signals are internally synchronized to the clock signals. The integrated signal delay blocks can be used to achieve phase alignment, controlled phase offsets between system reference and clock signals and to align/delay individual output signals. The four redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility.
The device is configured through a 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via the GPIO[1:0] outputs. Internal status bit changes can also be reported via a GPIO output.
For information regarding evaluation boards and material, please contact your local sales representative.