概览
描述
The 9ZML1253E is a second-generation enhanced performance DB1200ZL derivative. The part is a pin-compatible upgrade to the 9ZML1232B while offering a much-improved phase jitter performance. Fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.
特性
- SMBus write lock feature; increases system security
- 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
- LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
- 12 OE# pins; hardware control of each output
- 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
- Selectable PLL bandwidths; minimize jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz PLL mode; UPI support
- 10mm x 10mm 72-VFQFPN package; small board footprint
产品对比
应用
设计和开发
开发板与套件
评估
EVK9ZXL1951D
有效
Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI
The evaluation board is designed to help the customer evaluate the 9ZXL1951D. The device is programmable through an SMBus interface. The user guide details the board set and connection, as well as the companion Graphical User Interface (GUI) installation for communicating with the device. The...
模型
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视频和培训
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List
