Renesas 的时钟分频器（时钟频率分频器）提供的输出时钟信号是输入频率的分频。该时钟分频器也可用作时钟缓冲器，提供多个输出频率副本。时钟分频器用于 divide-by-1 模式时也能作为扇出缓冲器。
Renesas 的 8 系列扇出缓冲和时钟分频器采用全差分内部架构，即便单端I/O 器件也如此，这不仅能减少因内在共模噪声抑制造成的抖动，还能降低输出偏移。差分电路电流恒定，因此相对于单端解决方案而言注入系统的电源噪声更低，从而减小了 EMI 合规性方面的问题。
视频和培训
Overview of IDT's single-ended fanout buffers and single-ended fanout dividers. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. The clock fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about Renesas's rich portfolio of clock IC timing solutions, visit the Clock Buffers & Drivers page.