概览
描述
The IDT91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.
特性
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Zero input - output delay
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Frequency range 10 - 133 MHz (3.3V)
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5V tolerant input REF
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High loop filter bandwidth ideal for Spread Spectrum applications.
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Less than 125 ps cycle to cycle Jitter
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Skew controlled outputs
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Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm TSSOP packages
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Skew: Group-to-Group: <215 ps
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Skew within Group: <100 ps
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Commercial temperature range: 0°C to +70°C
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应用
设计和开发
模型
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