概览
描述
The 8T49N286 has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8kHz to 1GHz. Output frequencies can be completely independent of the input frequencies, and up to four of these frequencies can be completely independent of each other. The eight outputs may be selected among LVPECL, LVDS, HCSL, or LVCMOS output levels.
The 8T49N286 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or in test and measurement applications. For example, the 8T49N286 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card.
Renesas' third-generation Universal Frequency Translator family also includes the 8T49N285 (2-in/1-PLL/8-out), and 8T49N287 (2-in/2-PLL/8-out), and the 8T49N242 (2-in/1-PLL/4-out). These devices are complemented by the 82P33714 and 82P33731 SETS for Synchronous Ethernet (SyncE) and 10G to 40G SyncE, respectively.
特性
- Supports GR.1244 Stratum 3 stability in holdover mode
- Compliant with the requirements outlined in Telcordia GR-253-CORE (SONET) and ITU-T G.813/G.8262 (SDH/SONET and SyncE) when paired with a Synchronous Equipment Timing Source (SETS) device
- Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks ranging from 8kHz up to 1.0GHz (diff), 8kHz to 250MHz (LVCMOS), that meet jitter limits for 10G up to 100G Ethernet and STM-256/OC-768 applications
- 0.3ps RMS (including spurs), 12kHz to 20MHz
- Accepts up to four LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS input clocks ranging from 8kHz up to 875MHz
- Auto and manual input clock selection with hitless switching
- Clock input monitoring, including support for gapped clocks
- Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients
- Operates from a 10MHz to 40MHz fundamental-mode crystal
- Register programmable through I2C/SPI or via external I2C EEPROM
- 8T49N286-998 "boot from EEPROM"
- 8T49N286-999 "powers up disabled"
- Supported by the Timing™ Commander Software
产品对比
应用
- OTN or SONET/SDH equipment Line cards (Up to OC-192, and supporting FEC ratios)
- OTN de-mapping (Gapped Clock and DCO mode)
- Gigabit and Terabit IP switches/routers including support of Synchronous Ethernet
设计和开发
软件与工具
软件与工具
Software title
|
Software type
|
公司
|
---|---|---|
Timing Commander Timing Commander™ 是一个基于 Windows™ 的创新软件平台,通过这个平台,系统设计工程师可以通过直观且灵活的图形用户界面 (GUI) 对精密的计时设备进行配置、编程和监控。
|
Code Generator | 瑞萨电子 |
1 item
|
开发板与套件
模型
ECAD 模块
点击产品选项表中的产品,查找 SamacSys 中的原理图符号、PCB 足迹和 3D CAD 模型。点击产品选项表中的产品,查找 SamacSys 中的原理图符号、PCB 足迹和 3D CAD 模型。

产品选项
当前筛选条件
视频和培训
Description
Transcript
新闻和博客
Benefits of a Point-of-Use Clock for Jitter Optimization | 博客 | 2021年4月27日 |