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Monolithic Quad SPST, CMOS Analog Switches

封装信息

CAD 模型: View CAD Model
Pkg. Type: CERDIP
Pkg. Code: FBF
Lead Count (#): 16
Pkg. Dimensions (mm): 19.30 x 7.32 x 0.00
Pitch (mm): 2.54

环境和出口类别

Moisture Sensitivity Level (MSL) Not Applicable
Pb (Lead) Free No
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Pkg. Type CERDIP
Lead Count (#) 16
Carrier Type Tube
Moisture Sensitivity Level (MSL) Not Applicable
Pb (Lead) Free No
Pb Free Category Hot Solder Dip
MOQ 500
Temp. Range (°C) -55 to +125°C
CAGE code 34371
Advanced Features Low RON
Charge Injection (pC) 5
Die Sale Availability? No
Drain Capacitance 35
Flow Harsh Environment & MIL-STD-883
IS (mA) 0.1
Leakage (nA) 0.1
Length (mm) 19.3
PROTO Availability? No
Pitch (mm) 2.5
Pkg. Dimensions (mm) 19.3 x 7.3 x 0.00
Qualification Level Class Q
RDS (ON) (Ohms) 25
RON (max) (ohms) 25
Rating MIL-STD-883
Source Cap (pf) 9
Supply Voltage (max) (V) 20 - 20
Supply Voltage (min) (V) -20 - -20
Switch or MUX Switch
Switches (#) 4
TOFF (ns) 100
TON (ns) 110
Turn-Off Time (max) (ns) 160
Turn-On Time (max) (ns) 400
Type of Switch SPST
Width (mm) 7.3

描述

The DG411/883 series monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and CMOS compatible digital inputs. These switches feature lower analog ON-resistance (35Ω) and faster switch time (tON 175ns) compared to the DG211 or DG212. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG411/883 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. The power supplies may be single-ended from +5V to +34V, or split from ±5V to ±20V. The four switches are bilateral, equally matched for AC or bidirectional signals. The ON-resistance variation with analog signals is quite low over a ±15V analog input range. This permits independent control of turn-on and turn-off times for SPDT configurations, permitting “break-before-make” or “make-before-break” operation with a minimum of external logic.