概览
描述
The FCI FC8080 chip is a highly integrated device for Terrestrial Digital Multimedia Broadcasting (T-DMB). FC8080 has all of the performance needed to enable the full range of T-DMB applications. It consists of two main blocks, an RF tuner and channel decoder.
The RF block supports single-band (Band-III). It is a highly integrated component working with a single 1.2V power supply. Because direct-conversion architecture is used in the RF block, additional components such as a bulky IF SAW filter and other IF matching components are no longer required. For the direct-conversion, it has low noise fractional-N type frequency synthesizer and VCO. The RF block contains a Low Noise Amplifier (LNA), down-conversion mixer, Channel Selection Filter (CSF), and LO distribution network for Band-III.
The baseband block is an integrated circuit that provides a channel decoder for Digital Multimedia Broadcasting (DMB) signals based on ETS 300 401 (EUREKA-147). It is also in compliance with the function of Korea DAB/DMB (TTAS.KO -07.0024 and TTAS.KO-07.0026) standard. It contains a 10-bit Analog-to-Digital Converter (ADC) for IF input, OFDM demodulator, Reed Solomon decoder, and convolutional de-interleaver for providing forward error correcting. For audio data, it uses an MPEG I/II Layer II (MUSICAM) algorithm. It provides EBI2 LCD Interface of Qualcomm QSC series modem chip, SPI and I2C as a HOST interface. When it is used, I2C is the host interface, serial TS interface is also supported for data transmission.
特性
- Highly integrated digital device for DAB receiver (Eureka 147)
- Korea DAB/DMB (TTAS.KO -07.0024 and TTAS.KO-07.0026) standard compliant
- DAB OFDM channel demodulator and decoder
- Fully integrated, supports all DAB functions and modes (I, II, III, and IV)
- Mode detection (AMD)
- Full data rate of 1.8Mbit can be decoded
- Automatic frame and time synchronization and fast channel re-acquisition
- Digital AGC with a wide gain control range
- Demodulation and decoding of up to 64 sub-channels (UEP/EEP) TII decoder
- Automatic multiplex re-configuration
- Integrated high-density SRAM supporting time and frequency de-interleaving
- Simple memory concept. Do not require external memory for DAB operation
- Interfaces
- Parallel host interface
- 3-bit control pins, 4-bit data bus, it is compatible with Qualcomm QSC series modem chip
- Serial host interface
- SPI: up to 38.4MHz
- I2C: up to 1.0MHz for control and up to 38.4MHz serial TS interface for data
- Support max. 4 services (audio, video and data stream) of data service
- MPEG-2 Serial-TS output
- Various TS clock: 1.024MHz ~ 38.4MHz
- Be able to decode 2 video data with RS encoded stream
- Automatically internal hardware reset drive without external reset pin
- Parallel host interface
- Parallel host interface
- 3-bit control pins, 4-bit data bus, it is compatible with Qualcomm QSC series modem chip
- Serial host interface
- SPI: Up to 38.4MHz
- I2C: Up to 1.0MHz for control and up to 38.4MHz serial TS interface for data
- MPEG-2 Serial-TS output
- Various TS clock: 1.024MHz ~ 38.4MHz
- Electrical characteristics
- Embedded LDO for power
- Supply voltages: 1.2V for core and 1.8/2.5/3.3V for I/O
- Low power consumption: 20mA typical at core 1.2V
- Various power consumption management devices for this application
- Zero IF support
- Support various external clock
- Band frequency
- Band-III: 170MHz ~ 215MHz
- Sensitivity: -104.5dBm
- Noise figure: 2.7dB
- Adjacent channel sensitivity: 50dB typical
- Far off sensitivity: 55dB typical
- Band frequency
- Band-III: 170MHz ~ 215MHz
- Sensitivity: -104.5dBm
- Noise figure: 2.7dB
- Adjacent channel sensitivity: 50dB typical
- Far off sensitivity: 55dB typical
- Packages
- 25-pin WLCSP package with 2.14 x 2.09mm2
- 32-pin QFN package with 4 x 4mm2
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