概览
描述
The FC8150 chip is a highly integrated device for receiving Integrated Services Digital Broadcasting Terrestrial (ISDB-T). FC8150 has all of the performance needed to enable the full range of ISDB-T applications. It consists of two main blocks, an RF tuner and a demodulator.
The RF tuner block is designed for use in Japanese and Brazilian mobile digital TV (ISDB-T single-segment) applications. This part directly converts UHF band signals to a low-IF using a broadband down-converter. It contains LNA, down-conversion mixer, channel selection filter (CSF), and LO distribution network for UHF band.
The demodulator block (OFDM decoder) is part of a receiver for digital terrestrial television broadcast in accordance with the ISDB-T Japanese standard (STD-B31), which has all necessary functions for 1-segment mobile receiving. Designed by our unique synchronization and equalization technologies oriented toward mobile receiving, it gives good performances for high-speed moving applications. It is also suitable for cellular phone usage with its low power consumption and ultra-compact package size.
特性
- Highly integrated digital device for ISDB-T
- External specification
- Package
- 32-leads QFN (0.4mm pin pitches, 4.0mm x 4.0mm x 0.85mm)
- 48-balls fBGA (0.4mm ball pitches, 0.25mm ball diameter, 3.2mm x 3.2mm x 0.8mm)
- 34-balls WLCSP (0.35mm ball pitches, 0.1mm ball diameter, 2.3mm x 2.3mm x 0.35mm)
- Multi clock correspondence:
- Support clock (MHz): 16, 16.384, 18, 19.2, 24, 24.576, 26, 27, 27.12, 32, 37.4, 38.4MHz
- Recommended clock (MHz): 16.384, 24.576, 26.0, 32.0
- Power supply voltage: 1.14 ~ 1.32V (Core)/ 1.62 ~ 3.63V (I/O)/ 1.14 ~ 1.32V (RF,ADC)
- Power consumption: 31mW at Core 1.2V
- High-speed channel search function
- Mode, GI automatic detection
- Automatic frequency synchronization function
- Automatic timing synchronization function
- Embedded memory for time de-interleave
- Enhanced channel estimator by using accurate Doppler frequency measurement
- ICI canceller for enhancing the mobility performance
- Enhanced interference rejection technique
- Advanced demapper
- Complex low IF and digital PGA technology for simplified analog front-end path
- Sensitivity: -100dBm at QPSK CR=2/3
- Package
- Package
- 32-leads QFN (0.4mm pin pitches, 4.0mm x 4.0mm x 0.85mm)
- 48-balls fBGA (0.4mm ball pitches, 0.25mm ball diameter, 3.2mm x 3.2mm x 0.8mm)
- 34-balls WLCSP (0.35mm ball pitches, 0.1mm ball diameter, 2.3mm x 2.3mm x 0.35mm)
- Multi clock correspondence:
- Support Clock (MHz): 16, 16.384, 18, 19.2, 24, 24.576, 26, 27, 27.12, 32, 37.4, 38.4MHz
- Recommended Clock (MHz): 16.384, 24.576, 26.0, 32.0
- Interface
- Parallel host interface
- 3-bit control pins, 2-bit address bus and 8-bit data bus
- 3-bit control pins, 8-bit data bus, it is compatible with Qualcomm QSC/MSM series modem chip.
- Serial host interface
- SPI: Clock speed is up to crystal clock (max. 38.4MHz)
- I2C: Clock speed is up to 1.2MHz for control
- MPEG-2 Serial-TS output
- Various TS clock: Clock speed be controlled from crystal clock to 1/7 of crystal clock
- Interrupt signal output
- Parallel host interface
- Parallel host interface
- 3-bit control pins, 2-bit address bus and 8-bit data bus
- 3-bit control pins, 8-bit data bus, it is compatible with Qualcomm QSC/MSM series modem chip
- Serial host interface
- SPI: Clock speed is up to crystal clock (max. 38.4MHz)
- I2C: Clock speed is up to 1.2MHz for control
- MPEG-2 Serial-TS output
- Various TS clock: Clock speed be controlled from crystal clock to 1/7 of crystal clock
- 1-Segment reception (Japanese standard: ARIB STD-B31)
- Mode: 1, 2, 3
- Sub-carrier modulation: QPSK, 16QAM
- Code rate: QPSK (1/2, 2/3), 16QAM (1/2, 2/3)
- Frequency de-interleaving
- Time de-interleaving
- Viterbi decoder
- Byte de-interleaving (Forney type convolutional interleaver (I,M)=(12,17))
- Reed-Solomon decoder (204,188)
- Supported bandwidth: 6/7/8MHz
- Supported frequency bands
- UHF: 470~806MHz
- Supported frequency bands
- UHF: 470~806MHz
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设计和开发
模型
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