封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SOICW |
| Pkg. Code: | MEW |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 10.34 x 7.52 x 0.20 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.33.0001 |
| RoHS (HA9P5320-5Z) | 下载 |
产品属性
| Lead Count (#) | 16 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 3 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 10.3 x 7.5 x 0.20 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| MOQ | 480 |
| Temp. Range (°C) | 0 to +70°C |
| Country of Assembly | PHILIPPINES |
| Country of Wafer Fabrication | UNITED STATES |
| AVOL (dB) | 126 |
| Bandwidth (MHz) | 2 |
| CAGE code | 34371 |
| Die Sale Availability? | No |
| Droop Rate (μV/μs) | 0.08 |
| Flow | Harsh Environment & MIL-STD-883 |
| Hold Step Error (mV) | 5 |
| IBIAS (nA) | 70 |
| Lead Compliant | No |
| Length (mm) | 10.3 |
| Max Acquisition Time (10V Step to 0.01%) (μs) | 1.5 |
| Max Acquisition Time (10V Step to 0.1%) (μs) | 1.2 |
| Maximum Drift Current Over Temperature (nA) | 10 |
| PROTO Availability? | No |
| Pkg. Type | SOICW |
| Price (USD) | $19.83883 |
| Qualification Level | Standard |
| Rating | Harsh Environment |
| Requires External Hold Capacitor | Yes |
| Tape & Reel | No |
| Thickness (mm) | 0.2 |
| VOS (mV) | 0.2 |
| Width (mm) | 7.5 |
| tACQ (ns) | 1000 |
有关 HA-5320 的资源
描述
The HA-5320 was designed for use in precision, High-Speed data acquisition systems. The circuit consists of an input transconductance amplifier capable of providing large amounts of charging current, a low leakage analog switch, and an output integrating amplifier. The analog switch sees virtual ground as its load; therefore, charge injection on the hold capacitor is constant over the entire input/output voltage range. The pedestal voltage resulting from this charge injection can be adjusted to zero by use of the offset adjust inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time, additional hold capacitance may be added externally. This monolithic device is manufactured using the Intersil Dielectric Isolation Process, minimizing stray capacitance and eliminating SCRs. This allows higher speed and latchfree operation. For further information, please see Application Note AN538.