封装信息
| Lead Count (#) | 44 |
| Pkg. Code | QAH |
| Pitch (mm) | 0.8 |
| Pkg. Type | MQFP |
| Pkg. Dimensions (mm) | 10.01 x 10.01 x 2.02 |
环境和出口类别
| Pb (Lead) Free | No |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0030 |
| Moisture Sensitivity Level (MSL) |
产品属性
| Lead Count (#) | 44 |
| Carrier Type | Tray |
| Pb (Lead) Free | No |
| Temp. Range (°C) | -40 to +85°C |
| Channels (#) | 2 |
| Conversion Rate (Max) (kSPS) | 60000 |
| Differential NonLinearity LSB | 1 |
| Digital Supply Voltage (V) | 3 - 3 |
| Input BW (MHz) | 250 |
| Input VIN ((VPP, differential)) | 1 |
| Integral NonLinearity LSB | 2 |
| Interface | CMOS |
| Length (mm) | 10 |
| MOQ | 96 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 2.02 |
| Pkg. Type | MQFP |
| Power Consumption (mW) | 650 |
| Qualification Level | Standard |
| Resolution (bits) | 10 |
| SFDR (dB) (dB) | 70 |
| SNR (dbFS) | 54.7 |
| Supply Voltage (V) | 5 - 5 |
| Thickness (mm) | 2.02 |
| Width (mm) | 10 |
有关 HI5762 的资源
描述
Support is limited to customers who have already adopted these products.
The HI5762 is a monolithic, dual 10-bit, 60MSPS analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. Built by combining two cores of the HI5767 single channel 10-bit 60MSPS analog-to-digital converter, the HI5762 reaches a new level of multi-channel integration. The fully pipeline architecture and an innovative input stage enable the HI5762 to accept a variety of input configurations, single-ended or fully differential. Only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. This allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI5762 has excellent dynamic performance while consuming only 650mW of power at 60MSPS. The A/D only requires a single +5V power supply and encode clock. Data output latches are provided which present valid data to the output bus with a latency of 6 clock cycles. For those customers needing dual channel 8-bit resolution, please refer to the HI5662. For single channel 10-bit applications, please refer to the HI5767.