封装信息
| Lead Count (#) | 8 |
| Pkg. Code | MBY |
| Pitch (mm) | 1.27 |
| Pkg. Type | SOICN |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 1.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) |
产品属性
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range | -40 to +85°C |
| Bias Voltage Range (V) | 5 - 5 |
| IS (Typical) | 3.2 mA |
| Input Voltage (Max) (V) | 5 |
| Input Voltage (Max) [Rail 1] (V) | 5 - 5 |
| Input Voltage (Min) (V) | 2.5 |
| Input Voltage (Min) [Rail 1] (V) | 2.5 |
| Length (mm) | 4.9 |
| MOQ | 2500 |
| Output Voltage (Max) (V) | 5 |
| Output Voltage (Min) (V) | 0.8 |
| Output Voltage (Min) [Rail 1] (V) | 0.8 |
| Parametric Category | Buck Controllers (External FETs) |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 0.00 |
| Pkg. Type | SOICN |
| Qualification Level | Standard |
| Thickness (mm) | 0 |
| Topology [Rail 1] | Buck |
| VBIAS (Max) (V) | 5 |
| VBIAS (Min) (V) | 5 |
| Width (mm) | 3.9 |
描述
The ISL6520A makes simple work out of implementing a complete control and protection scheme for a DC/DC stepdown converter. Designed to drive N-Channel MOSFETs in a synchronous buck topology, the ISL6520A integrates the control, output adjustment, monitoring and protection functions into a single 8 Lead package. The ISL6520A provides simple, single feedback loop, voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0. 8V, with a maximum tolerance of ±1. 5% over-temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 8V/ms slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor.