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描述

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The ISL8200MMREP is a simple and easy to use high power, current-sharing DC/DC power module for Datacom/Telecom/FPGA power hungry applications. All that is needed is the ISL8200MMREP, a few passive components and one VOUT setting resistor to have a complete 10A design ready for market. The ease of use virtually eliminates the design and manufacturing risks while dramatically improving time to market. Need more output current? Just simply parallel up to six ISL8200MMREP modules to scale up to a 60A solution (see Figure 6 on page 10). The simplicity of the ISL8200MMREP is in its “Off The Shelf”, unassisted implementation. Patented current sharing in multiphase operation greatly reduces ripple currents, BOM cost and complexity. For example, parallel 2 for 20A and up to 6 for 60A. The output voltage can be precisely regulated to as low as 0. 6V with ±1% output voltage regulation over line, load, and temperature variations. The ISL8200MMREP’s thermally enhanced, compact QFN package, operates at full load and over-temperature, without requiring forced air cooling. It's so thin it can even fit on the back side of the PCB. Easy access to all pins with few external components, reduces the PCB design to a component layer and a simple ground layer.

特性

  • Specifications per DLA VID V62/10608
  • Full mil-temp electrical performance from -55°C to +125°C
  • Full traceability through assembly and test by date/trace code assignment
  • Enhanced process change notification
  • Enhanced obsolescence management
  • Complete switch mode power supply in one package
  • Patented current share architecture reduces layout sensitivity when modules are paralleled
  • Programmable phase shift (1, 2, 3, 4, and 6 phase)
  • Extremely low profile (2.2mm height)
  • Input voltage range +3.0V to +20V at 10A, current share up to 60A
  • A Single resistor sets VOUT from +0.6V to +6V
  • Output overvoltage, overcurrent and over-temperature, built-in protection and undervoltage indication

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应用

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软件与工具

软件下载

类型 文档标题 日期
PCB 设计文件 ZIP 251 KB
PCB 设计文件 ZIP 1022 KB
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