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VCSO FEC PLL For SONET/OTN

封装信息

Pkg. Type: CLCC
Pkg. Code: CG36
Lead Count (#): 36
Pkg. Dimensions (mm): 9.0 x 9.0 x 2.8
Pitch (mm): 0.6

环境和出口类别

Pb (Lead) Free Yes
Moisture Sensitivity Level (MSL) 1
ECCN (US)
HTS (US)

产品属性

Pkg. Type CLCC
Lead Count (#) 36
Pb (Lead) Free Yes
Carrier Type Reel
Abs. Pull Range Min. (± PPM) 120
Core Voltage (V) 3.3
Feedback Input No
Input Freq (MHz) 10 - 700
Input Type LVCMOS, LVPECL, LVDS
Inputs (#) 2
Length (mm) 9
MOQ 500
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 2
Output Freq Range (MHz) 20.9165 - 20.9165, 83.6658 - 83.6658, 167.332 - 167.332, 669.327 - 669.327
Output Type LVPECL
Output Voltage (V) 3.3
Outputs (#) 2
Package Area (mm²) 81
Pb Free Category e4 Au
Phase Jitter Max RMS (ps) 0.5
Phase Jitter Typ RMS (ps) 0.25
Pitch (mm) 0.6
Pkg. Dimensions (mm) 9.0 x 9.0 x 2.8
Prog. Clock No
Qty. per Carrier (#) 0
Qty. per Reel (#) 500
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Temp. Range (°C) 0 to 70°C
Thickness (mm) 2.8
Width (mm) 9
已发布 No

描述

The M2060/61/62 and M2065/66/67 are Voltage Controlled SAW Oscillator (VCSO) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support Forward Error Correction (FEC) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.