瑞萨电子 (Renesas Electronics Corporation)
搜索

5P49V5933 (VersaClock® 5) Custom Part Configuration Utility

The 5P49V5933 features an integrated 25 MHz crystal, redundant external clock input, and two programmable outputs. The device can store up to four configurations selectable using the SEL pins. Use the form below to configure outputs for each configuration used.

IMPORTANT NOTE: In order to minimize sample delivery times, all outputs will be configured to provide RMS phase jitter performance of 1.5 ps or less (12 kHz to 20 MHz integration range). If lower phase jitter is required, please provide the requirements in the comment box located at the bottom of this form.

方框图

diagram

Timing Commander Configuration File Upload (optional)

Use this form to upload your Timing Commander configuration file for the 5P49V5933 part. This will disable the configurator below. The datasheet addendum will be provided by Renesas after review.

Configuration File (.tcs) Uploader

Global Configuration

Choose the number of configurations to program into the part. It will support up to four different configurations selectable using the SEL pins. Configurations
Selects the I2C address of the device. Up to 2 addresses are supported, allowing use of more than one VersaClock 5 on the same I2C bus. I2C Address
Selects the function of the SD/OE pin: either Shutdown or Output Enable. Selects the default status of the output (on or off) at startup. SD / OE Function
If SD/OE pin is set as Output Enable, this setting determines the polarity of the input pin (active High or active Low.) SD / OE Polarity

Configuration 0

Input

Input frequency to the device when using a external differential input clock. Valid range is 1 MHz-to-350 MHz. Leave this setting at 25 MHz if not planning to use an external clock. Input Frequency CLKIN (MHz)

Input Configuration Defines the behavior of the CLKSEL pin when Low, Open, and High. The CLKSEL input pin selects either the crystal input or the differential clock input. Note that the differential clock input can be wired to accept single-ended signals.

Input when CLKSEL = LOW or OPEN Input when CLKSEL = HIGH
Integrated crystal as input None (differential clock input disabled)
Integrated crystal as input Differential clock input
Differential clock input Integrated crystal as input

Output

参数 Output 0 (Buffer) Output 1 Output 2
Output frequency. Valid range is 1 MHz-to-200 MHz for single-ended signaling and 1 MHz-to-350 MHz for differential signaling. Frequency (MHz)
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I²C or OE/SD (depending on configuration). Selecting 'Unused Output\' completely disables the output and associated circuitry. When OE is OFF, the outputs are OFF. Output Enable

Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

Note: HCSL and LVPECL outputs support a VDDO Voltage of 2.5 V or 3.3 V only. Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

 Output Type

Power supply voltage (VDDO) of output. Determines the output signal's high and low voltages.

Note: 1.8 V is not compatible with HCSL or LVPECL Output Type. Power supply voltage (VDDO) of output x. Determines the output signal's high and low voltages.

 Voltage (V)
Enables spread spectrum on output, either as down spread (frequency modulation is below output nominal frequency), or as center spread (frequency modulation is below and above output nominal frequency). Spread Spectrum
The rate at which the output frequency is modulated over the selected spread percentage. Spread Modulation Freq (kHz)
Selects the amount of spread spectrum modulation on output. Valid ranges are -0.5% to -5% for down spread, and ±0.25% to ±2.5% for center spread. Spread (%)
Enables a reduced slew rate on output down to 0.8x the nominal rate. Slew Rate
Selects phase shift of output in relation to other outputs. Enter the number of degrees from 0 to 360. Phase shift (Degrees)

Configuration 1

Copy from Configuration 0

Input

Input frequency to the device when using a external differential input clock. Valid range is 1 MHz-to-350 MHz. Leave this setting at 25 MHz if not planning to use an external clock. Input Frequency CLKIN (MHz)

Input Configuration Defines the behavior of the CLKSEL pin when Low, Open, and High. The CLKSEL input pin selects either the crystal input or the differential clock input. Note that the differential clock input can be wired to accept single-ended signals.

Input when CLKSEL = LOW or OPEN Input when CLKSEL = HIGH
Integrated crystal as input None (differential clock input disabled)
Integrated crystal as input Differential clock input
Differential clock input Integrated crystal as input

Output

参数 Output 0 (Buffer) Output 1 Output 2
Output frequency. Valid range is 1 MHz-to-200 MHz for single-ended signaling and 1 MHz-to-350 MHz for differential signaling. Frequency (MHz)
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I²C or OE/SD (depending on configuration). Selecting 'Unused Output\' completely disables the output and associated circuitry. When OE is OFF, the outputs are OFF. Output Enable

Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

Note: HCSL and LVPECL outputs support a VDDO Voltage of 2.5 V or 3.3 V only. Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

 Output Type

Power supply voltage (VDDO) of output. Determines the output signal's high and low voltages.

Note: 1.8 V is not compatible with HCSL or LVPECL Output Type. Power supply voltage (VDDO) of output x. Determines the output signal's high and low voltages.

 Voltage (V)
Enables spread spectrum on output, either as down spread (frequency modulation is below output nominal frequency), or as center spread (frequency modulation is below and above output nominal frequency). Spread Spectrum
The rate at which the output frequency is modulated over the selected spread percentage. Spread Modulation Freq (kHz)
Selects the amount of spread spectrum modulation on output. Valid ranges are -0.5% to -5% for down spread, and ±0.25% to ±2.5% for center spread. Spread (%)
Enables a reduced slew rate on output down to 0.8x the nominal rate. Slew Rate
Selects phase shift of output in relation to other outputs. Enter the number of degrees from 0 to 360. Phase shift (Degrees)

Configuration 2

Copy from Configuration 0

Input

Input frequency to the device when using a external differential input clock. Valid range is 1 MHz-to-350 MHz. Leave this setting at 25 MHz if not planning to use an external clock. Input Frequency CLKIN (MHz)

Input Configuration Defines the behavior of the CLKSEL pin when Low, Open, and High. The CLKSEL input pin selects either the crystal input or the differential clock input. Note that the differential clock input can be wired to accept single-ended signals.

Input when CLKSEL = LOW or OPEN Input when CLKSEL = HIGH
Integrated crystal as input None (differential clock input disabled)
Integrated crystal as input Differential clock input
Differential clock input Integrated crystal as input

Output

参数 Output 0 (Buffer) Output 1 Output 2
Output frequency. Valid range is 1 MHz-to-200 MHz for single-ended signaling and 1 MHz-to-350 MHz for differential signaling. Frequency (MHz)
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I²C or OE/SD (depending on configuration). Selecting 'Unused Output\' completely disables the output and associated circuitry. When OE is OFF, the outputs are OFF. Output Enable

Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

Note: HCSL and LVPECL outputs support a VDDO Voltage of 2.5 V or 3.3 V only. Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

 Output Type

Power supply voltage (VDDO) of output. Determines the output signal's high and low voltages.

Note: 1.8 V is not compatible with HCSL or LVPECL Output Type. Power supply voltage (VDDO) of output x. Determines the output signal's high and low voltages.

 Voltage (V)
Enables spread spectrum on output, either as down spread (frequency modulation is below output nominal frequency), or as center spread (frequency modulation is below and above output nominal frequency). Spread Spectrum
The rate at which the output frequency is modulated over the selected spread percentage. Spread Modulation Freq (kHz)
Selects the amount of spread spectrum modulation on output. Valid ranges are -0.5% to -5% for down spread, and ±0.25% to ±2.5% for center spread. Spread (%)
Enables a reduced slew rate on output down to 0.8x the nominal rate. Slew Rate
Selects phase shift of output in relation to other outputs. Enter the number of degrees from 0 to 360. Phase shift (Degrees)

Configuration 3

Copy from Configuration 0

Input

Input frequency to the device when using a external differential input clock. Valid range is 1 MHz-to-350 MHz. Leave this setting at 25 MHz if not planning to use an external clock. Input Frequency CLKIN (MHz)

Input Configuration Defines the behavior of the CLKSEL pin when Low, Open, and High. The CLKSEL input pin selects either the crystal input or the differential clock input. Note that the differential clock input can be wired to accept single-ended signals.

Input when CLKSEL = LOW or OPEN Input when CLKSEL = HIGH
Integrated crystal as input None (differential clock input disabled)
Integrated crystal as input Differential clock input
Differential clock input Integrated crystal as input

Output

参数 Output 0 (Buffer) Output 1 Output 2
Output frequency. Valid range is 1 MHz-to-200 MHz for single-ended signaling and 1 MHz-to-350 MHz for differential signaling. Frequency (MHz)
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I²C or OE/SD (depending on configuration). Selecting 'Unused Output\' completely disables the output and associated circuitry. When OE is OFF, the outputs are OFF. Output Enable

Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

Note: HCSL and LVPECL outputs support a VDDO Voltage of 2.5 V or 3.3 V only. Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).

 Output Type

Power supply voltage (VDDO) of output. Determines the output signal's high and low voltages.

Note: 1.8 V is not compatible with HCSL or LVPECL Output Type. Power supply voltage (VDDO) of output x. Determines the output signal's high and low voltages.

 Voltage (V)
Enables spread spectrum on output, either as down spread (frequency modulation is below output nominal frequency), or as center spread (frequency modulation is below and above output nominal frequency). Spread Spectrum
The rate at which the output frequency is modulated over the selected spread percentage. Spread Modulation Freq (kHz)
Selects the amount of spread spectrum modulation on output. Valid ranges are -0.5% to -5% for down spread, and ±0.25% to ±2.5% for center spread. Spread (%)
Enables a reduced slew rate on output down to 0.8x the nominal rate. Slew Rate
Selects phase shift of output in relation to other outputs. Enter the number of degrees from 0 to 360. Phase shift (Degrees)

项目信息

Comments / Special Requests

提交此表格即表示您同意瑞萨电子将您提交的上述信息、数据和/或文档的全部或一部分在瑞萨电子集团内部分享以及与第三方（如分销商）分享，以便为您提供与我们的产品相关的更多信息和服务。 如果您不希望瑞萨电子共享您的信息，请勿单击提交按钮。 请参阅隐私政策以了解更多详情。