概览

描述

The RC38612 RAN synchronizer regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on wireless baseband, DU, CU, RU, fronthaul or backhaul networks. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generationi including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

特性

  • Six independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • IEEE 1588 Support:
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

应用

文档

文档标题 类型 日期
PDF1.90 MB
数据手册
PDF1.92 MB
应用文档
PDF1.16 MB
应用文档
PDF1.92 MB
应用文档
PDF2.13 MB
应用文档
PDF1.62 MB
应用文档
PDF354 KB
应用文档
PDF148 KB
应用文档
PDF390 KB
应用文档
PDF880 KB
应用文档
PDF584 KB
应用文档
PDF162 KB
应用文档
PDF739 KB
应用文档
PDF633 KB
应用文档
PDF479 KB
应用文档
PDF442 KB
应用文档
PDF566 KB
应用文档
PDF976 KB
应用文档
PDF659 KB
应用文档
PDF324 KB
应用文档
PDF43 KB
器件勘误表
PDF2.93 MB
指南
PDF10.53 MB
指南
PDF2.40 MB
指南
XLSX393 KB
其他
PDF320 KB
概览
PDF109 KB
产品变更通告
PDF301 KB
产品变更通告
PDF123 KB
产品变更通告
PDF435 KB
产品变更通告
PDF206 KB
原理图
PDF400 KB
白皮书

设计和开发

软件与工具

软件下载

文档标题 类型 日期
ZIP50.80 MB
软件和工具 - 其他
ZIP48.70 MB
软件和工具 - 其他
ZIP18.02 MB
软件和工具 - 其他
ZIP5 KB
软件和工具 - 其他
GZ264 KB
软件和工具 - 软件

开发板与套件

开发板与套件

模块

模块

Title Type Date
模型 - BSDL
模型 - BSDL
模型 - IBIS
模型 - IBIS

视频和培训

IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)

Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. 

They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

For more information, visit www.idt.com/clockmatrix.