XT

The XF and XP family of field-programmable clock oscillators (XOs) are optimized for use data centers, optical and wireline communication network, and industrial level equipment that demands very low noise, stable, and accurate timing/clock sources. These devices are single-output clock oscillators with an integrated resonator that utilizes a proprietary ASIC with a key focus on reduction in phase noise and phase jitter. Typical phase jitter is 120fs over 12kHz to 20MHz bandwidth. These chips are available in a wide frequency range from 15MHz to 2100MHz.

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• Crystal Oscillators

A brief overview of the features and benefits of IDT's (acquired by Renesas) ProXO family clock oscillators. These clock oscillators offer designers a reliable on-time, timing solution. Short lead-time, low noise, wide frequency range, excellent temperature versus frequency performance, and very little engineering effort for design in, makes them an excellent choice over conventional technology solutions. The clock oscillator families have stabilities as tight as ±20ppm, a range of phase jitter options, and temperature capabilities up to +105°C. These devices also offer extremely quick delivery for both standard and custom frequencies (16kHz to 2.1GHz).

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• Crystal Oscillators

IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

So, hi there, this is Ron Wade again and we're going to be talking about timing solutions that IDT has for NXP's QorIQ and Layerscape CPU. And in the middle here, what I've drawn, in the middle of the box here, is what I refer to as our all-in-one solutions. These are single chips that may have all the clocks you need to build your system around the NXP CPUs. So, the three parts I have listed here are the 6P49V205, the 5P49V5907, and 5P49V5908. These provide a mix of the clocks that were needed over here for the CPU cores and SerDes clocks, and they're all on a single chip. If these suit your needs, these are ideal, these are the smallest core footprint parts to use. 
 
The other approach besides all-in-one is the building block approach, and I'm going to start over here on the left side with the CPU clocks and the memory controller. For this solution over here, we have the 5P49V5901, or it could be a 6901, depending on your requirements. And, this guy has the most flexibility as far as programming up any combination of DDR clock or CPU clock that you want, as well as the 24 MHz USB clock and a 125 MHz clock. 
 
If you're using the Layerscape CPU with the reduced oscillator mode where you have the 100 MHz non-spread clock coming in, you might want to consider the 9FGV0 series or the 9FGL0 series. These are very high-performance PCI Express clock generators, the V being a 1.8 volt part and the L being a 3.3 volt part that are available. The terminations are integrated, they're very low power and they also have some extra copies in case SerDes is a PCI Express SerDes. So, this is the ideal solution if you want to go building block over here. 
 
And then for the SerDes clocks, we've got the 125 MHz differential for Gigabit Ethernet, the 156 MHz for 10 gig, and the 100 MHz for PCIe. We have again a different set of flavors we can go with. We have the 5P49V6901, which is a better performing, lower phase jitter version of the 5901 over here. This guy's ideal if you have a mix of these SerDes frequencies in your design. If you're in a homogeneous environment, for instance, where everything's PCI Express or everything is 125 MHz, then you could use the 9FGV parts, or I'll use an output from over there, over on this side for the 100 MHz output, or you could use these guys programmed up to be 125 as well. Or if you've got a 125 coming from over there, you can use one of the 9DVD buffers which are the 1.8V buffers to fan that out. Likewise, we have similar parts with 3.3-volt power supplies, if that's what you prefer. The 9FGL0 series, it should give you the 100 to the 125, and the 9DVL0 series which can provide a fanout buffer for any of these three frequencies.
 
So, that's an overview of the timing solutions for NXP's QorIQ and Layerscape CPUs. This is Ron Wade at IDT again. Thanks for watching and see you next time.

IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

Hi there, this is Ron Wade with IDT and today we're going to talk about NXP, formerly known as Freescale, CPUs. Specifically the QorIQ and Layerscape CPUs and the timing requirements that they have. So, it's basically divided into a couple of parts here. There's some timing that the CPU itself requires and then there's timing that depends upon your system and the number of SerDes links you have in your design and in your CPU. So, if we talk about the CPU part itself, we have the CPU cores which get a clock, and we have the memory controller inside the CPUs which gets a clock as well. And the memory controller clock is called the DDR clock. The CPU clock is called the SYS_CCB clock in the Freescale nomenclature, excuse me, the NXP nomenclature and those frequencies - they're single-ended clocks and they range, like the DDR from 66.66 MHz up to 100 MHz, and the CPU clocks range from 66.66 up to 133.33 MHz, in some cases. Those are single-ended LVCMOS input clocks. Additionally, some of the CPUs have a USB interface which may require a 24 MHz single-ended clock. And there's also an Ethernet interface built in, a one-gigabit Ethernet interface, that is, takes a 125 MHz single-ended clock as well and that's at 2.5 volts.
 
So, in the Layerscape series of CPUs which are based on the ARM core, Freescale has put into them, what they call a reduced oscillator mode where all the clocks over here basically are reduced by a single differential 100 MHz non-spreading clock, and this saves you from having to figure out and generate all these clocks. However, it has to be non-spread because the USB clock is also derived from it, so, if you're planning to use spread spectrum, you really can't use this mode. And, currently, it's only available in the Layerscape devices, not the legacy QorIQ devices.
 
So, that's the basics for the CPU and the memory controller. Then the SerDes is really dependent upon the particular CPU you're using and how many SerDes lanes you need in your design. So, the SerDes clocks, on the other hand, basically range from 125 MHz differential clock for Gigabit Ethernet, if you're using 10 Gigabit Ethernet, a 156.25 MHz clock is required. And then if you're using PCI Express, you'd use a standard 100 MHz PCI Express clock. All these happen to be differential and the number of SerDes lanes and their capabilities depends on the CPU you're using. So, this gives you an outline of how to just do a quick tally of what kind of clocks you need and in another video, I'll talk about the solutions that IDT has for NXP's devices.