概览

描述

The 70T3399 is a high-speed 128K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.

特性

  • Dual-Port allows simultaneous access of the same memory location
  • Selectable Pipelined or Flow-Through output mode
  • Counter enable and repeat features
  • Dual chip enables allow for depth expansion without additional logic
  • Interrupt and Collision Detection Flags
  • Full synchronous operation on both ports
  • Separate byte controls for multiplexed bus and bus matching compatibility
  • Dual Cycle Deselect (DCD) for Pipelined Output Mode
  • 2.5V (±100mV) power supply for core
  • LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
  • Available in a 256-pin BGA and 208-pin fpBGA packages
  • Includes JTAG functionality
  • Industrial temperature range (-40C to +85C) is available

文档

文档标题 类型 日期
PDF541 KB
数据手册
PDF198 KB
应用文档
PDF156 KB
应用文档
PDF225 KB
应用文档
PDF97 KB
应用文档
PDF154 KB
应用文档
PDF112 KB
应用文档
PDF70 KB
End Of Life Notice
PDF24 KB
产品变更通告
PDF194 KB
产品变更通告
PDF729 KB
产品变更通告
PDF290 KB
产品变更通告
PDF80 KB
产品变更通告
PDF38 KB
产品变更通告
PDF26 KB
产品变更通告
PDF197 KB
产品变更通告
PDF150 KB
产品变更通告
PDF65 KB
产品变更通告

设计和开发

软件与工具

软件下载

文档标题 类型 日期
PDF70 KB
End Of Life Notice

模块

模块

Title Type Date
模型 - BSDL
模型 - IBIS
模型 - VHDL
模型 - Verilog

支持