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3.3V Zero Delay Clock Buffer

封装信息

CAD 模型: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG8
Lead Count (#): 8
Pkg. Dimensions (mm): 3.1 x 4.4 x 1.0
Pitch (mm): 0.65

环境和出口类别

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 8
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2500
Qty. per Carrier (#) 0
Output Type LVCMOS
Package Area (mm²) 13.6
Pitch (mm) 0.65
Pkg. Dimensions (mm) 3.1 x 4.4 x 1.0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Accepts Spread Spec Input No
C-C Jitter Max P-P (ps) 200
Core Voltage (V) 3.3
Input Freq (MHz) 10 - 133
Input Type LVCMOS
Inputs (#) 1
Length (mm) 3.1
MOQ 2500
Multiply/Divide Value 1
Output Banks (#) 2
Output Freq Range (MHz) 10 - 133
Output Skew (ps) 250
Output Voltage (V) 3.3
Outputs (#) 5
Pkg. Type TSSOP
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4
已发布 No

描述

The 2305B is a high-speed phase-locked loop (PLL) clock buffer designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz. The 2305B is an 8-pin version of the 2309B. This device accepts one reference input and drives out five low-skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 2305B enters power down. In this mode, the device will draw less than 25μA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The 2305B is characterized for both industrial and commercial operation.