封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG16 |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 5.0 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 16 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 96 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | SINGAPORE |
| Advanced Features | Spread Spectrum |
| App Jitter Compliance | PCIe Gen1 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 80 |
| C-C Jitter Typ P-P (ps) | 65 |
| Core Voltage (V) | 3.3 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 2 |
| Diff. Termination Resistors | 8 |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| MOQ | 384 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 25 - 25, 100 - 100, 125 - 125, 200 - 200 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| PLL | Yes |
| Package Area (mm²) | 22 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 5.0 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Power Consumption Typ (mW) | 257 |
| Price (USD) | $1.94823 |
| Prog. Clock | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
| Xtal Freq (MHz) | 25 - 25 |
| 已发布 | No |
有关 557-03 的资源
描述
The 557-03 is a spread spectrum clock generator that supports PCI-Express Gen 1 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT's patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.