特性
- 1 - 0.7V current mode differential HCSL output pairs
- 16-pin QFN package
- very small board footprint
- Spread-spectrum capable
- reduces EMI
- Outputs can be terminated to LVDS
- can drive a wider variety of devices
- Spread enable via pin selection
- no software required to configure device
- Industrial temperature range available
- supports demanding embedded applications
- For PCIe Gen3 applications, see the 5V41234
- Cycle-to-cycle jitter < 100 ps
- PCIe Gen2 phase jitter < 3.0ps RMS
描述
The 5V41064 is a PCIe Gen2 compliant spread spectrum capable clock generator. The device has 1 differential HCSL output and can be used in communication or embedded systems to substantially reduce electro-magnetic interference (EMI). Spread spectrum can be enabled via a select pin.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.