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2:4 PCIe GEN1/2/3 Clock Multiplexer

封装信息

CAD 模型: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG20
Lead Count (#): 20
Pkg. Dimensions (mm): 6.5 x 4.4 x 1.0
Pitch (mm): 0.65

环境和出口类别

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 20
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 74
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Accepts Spread Spec Input Yes
Additive Phase Jitter Typ RMS (fs) 100
Additive Phase Jitter Typ RMS (ps) 0.1
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3
Architecture Common
Core Voltage (V) 3.3
Diff. Input Signaling HCSL
Diff. Inputs 2
Diff. Output Signaling HCSL
Diff. Outputs 4
Diff. Termination Resistors 16
Function Multiplexer
Input Freq (MHz) 200
Input Type HCSL
Inputs (#) 2
Length (mm) 6.5
MOQ 148
Output Banks (#) 1
Output Freq Range (MHz) 200
Output Skew (ps) 50
Output Type HCSL, LVDS
Output Voltage (V) 3.3
Outputs (#) 4
PLL No
Package Area (mm²) 28.6
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.5 x 4.4 x 1.0
Pkg. Type TSSOP
Power Consumption Typ (mW) 264
Price (USD) $11.80399
Prog. Clock No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Supply Voltage (V) 3.3 - 3.3
Tape & Reel No
Thickness (mm) 1
Width (mm) 4.4
已发布 No

描述

The 5V41067A is a 2:4 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41067A selects between 1 of 2 differential HCSL inputs to fanout to 4 differential HCSL output pairs. The outputs can also be terminated to LVDS.