概览
描述
The 5V41068A is a 2:1 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41068A selects between 1 of 2 differential HCSL inputs to drive a single differential HCSL output pair. The output can also be terminated to LVDS.
特性
- 1 – 0.7V current mode differential HCSL output pair
- Low additive jitter
- suitable for use in PCIe Gen2 and Gen3 systems
- 16-pin TSSOP package
- small board footprint
- Outputs can be terminated to LVDS
- can drive a wider variety of devices
- OE control pin
- greater system power management
- Industrial temperature range available
- supports demanding embedded applications
- Additive cycle-to-cycle jitter <5 ps
- Additive phase jitter (PCIe Gen3) <0.2ps
- Operating frequency up to 200MHz
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视频和培训
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
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