封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NXG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 1.5 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | MALAYSIA |
| Country of Wafer Fabrication | TAIWAN |
| Additive Phase Jitter Typ P-P (ps) | 1.5 |
| Advanced Features | Programmable Clock, Spread Spectrum |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common |
| C-C Jitter Typ P-P (ps) | 50 |
| Core Voltage (V) | 3.3V |
| Family Name | VersaClock 3S |
| Feedback Input | No |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal (integrated) |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| MOQ | 490 |
| NXP Processor Function | Memory Clock, SerDes Clock, CPU/USB/Eth Clock |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 0.032768 - 500 |
| Output Type | LVCMOS, LVPECL, LP-HCSL, LVDS |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Outputs (#) | 5 |
| Package Area (mm²) | 9 |
| Phase Jitter Typ RMS (ps) | 1 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.5 |
| Pkg. Type | VFQFPN |
| Price (USD) | $1.61747 |
| Prog. Clock | Yes |
| Prog. Interface | I2C, OTP |
| Reference Output | No |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Thickness (mm) | 1.5 |
| Width (mm) | 4 |
| Xtal Freq (MHz) | 25 - 25 |
| Xtal Inputs (#) | 1 |
| 已发布 | No |
有关 5X35023 的资源
描述
The 5X35023 VersaClock® programmable clock generator is designed for low-power, consumer, and high-performance PCI Express applications. The device is a three-PLL architecture design, and each PLL is individually programmable and allows for up to five unique frequency outputs.
The 5X35023 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshoot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5X35023 again through the I²C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pairs of differential outputs that support LVCMOS, LP-HCSL, LVDS, and LVPECL. A low-power 32.768kHz clock is supported with only less than 2μA current consumption for a system RTC reference clock.