概览
描述
The IDT 650-14 is a low cost, low jitter, high performance clock synthesizer customized for networking systems applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a 25 MHz clock or fundamental mode crystal input to produce multiple output clocks of one fixed 25 MHz, a four (plus one) frequency selectable bank, and two frequency selectable clocks. All output clocks are frequency locked together. The IDT650-14 outputs have zero ppm synthesis error.
特性
- Packaged in 20-pin SSOP
- 25 MHz fundamental crystal or clock input
- One fixed output clock of one 25 MHz
- One bank of four frequency selectable output clocks
- Three frequency selectable clock outputs
- Zero ppm synthesis error on all clocks
- Ideal for networking systems
- Full CMOS output swing
- Advanced, low power sub-micron CMOS process
- Operating voltage of 3.3 V or 5.0 V
- Industrial temperature range available
产品对比
应用
设计和开发
模型
ECAD 模块
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