瑞萨电子 (Renesas Electronics Corporation)
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5P35023

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产品长期供货

VersaClock 3S Programmable Clock Generator

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特性

  • Configurable OE pin function as OE, PD#, PPS, or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance Power Balancing feature allows minimum power consumption based on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 different frequencies to switch dynamically
  • Spread spectrum clock support to lower system EMI
  • I2C interface
  • Also supports crystal input
  • Available in AEC-Q100 qualified, Grade 2 (-40 °C to +105 °C) version
查找可编程时钟的其他产品
5P35023 - Block Diagram
5P35023 - Pinout
VersaClock 3S Low Power Programmable Clock Generators
5P35023 - Block Diagram
5P35023 - Pinout
VersaClock 3S Low Power Programmable Clock Generators

描述

The 5P35023 is a VersaClock® programmable clock generator designed for low-power, consumer, and high-performance PCI Express applications. The 5P35023 device is a three-PLL architecture design, and each PLL is individually programmable and allows for up to five unique frequency outputs. The 5P35023 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after powering up, and then program the 5P35023 again through the I2C interface.

The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports three single-ended outputs and two pairs of differential outputs that support LVCMOS, LVPECL, LVDS, and LPHCSL. A low-power 32.768kHz clock is supported with only less than 5μA current consumption for the system RTC reference clock.

产品对比

5P35023 5L35021 5L35023 5P35021
Outputs (#) 7 5 7 5
Output Type LP-HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 3.3 1.8 1.8 3.3
Output Voltage (V) 1.8, 2.5, 3.3 1.8 1.8 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 4.0 x 4.0 x 0.9 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9 3.0 x 3.0 x 1.0

产品参数

属性 值
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3
Outputs (#) 7
Output Type LVCMOS, LVPECL, LP-HCSL, LVDS
Output Freq Range (MHz) 0.032768 - 500
Input Freq (MHz) 1 - 160
Inputs (#) 1
Input Type Crystal, LVCMOS, LVPECL, LVDS, LP-HCSL
Output Banks (#) 5
Core Voltage (V) 3.3
Output Voltage (V) 1.8, 2.5, 3.3
Phase Jitter Typ RMS (ps) 3
Prog. Interface I2C, OTP
Spread Spectrum Yes

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 4.0 x 4.0 x 0.9 24 0.5

应用方框图

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高端功能丰富的 HMI 平台
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便携式 POS 终端
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基于 MPU 的单板计算机
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适用于低功耗蓝牙网状网络的网络网关
网关设计采用双核 MPU、低功耗蓝牙 Mesh、Wi-Fi、本地/云存储、警报和安全通信。
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此为出厂可配置设备。试用自定义部件配置工具。

当前筛选条件

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This video introduces IDT's VersaClock 3S Programmable Clock Generators, known for their innovative power-saving features and compact design that eliminates multiple timing components. Designed for applications in consumer, industrial, computing, and automotive sectors, these devices offer low power consumption and low jitter scalability, meeting PCI Express® Gen 1/2/3 standards. 

Key features highlighted include Proactive Power Saving, Performance-Power Balancing, Dynamic Frequency Control, and Overshoot Reduction Technology. The video showcases the VersaClock 3S models, including the 5P35023 with multiple outputs and the 5P35021 with a 32.768KHz clock for RTC reference, supported by IDT's Timing Commander software for easy programming.

新闻和博客

博客
2019年2月7日
The Value of Fractional Output Divider PLLs for Infotainment and Dashboard Applications
新闻
2016年5月31日
IDT’s New VersaClock 3S Clock Generators Deliver Innovative Features for Optimal Blend of Performance, Power and Flexibility
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