封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | QSOP |
| Pkg. Code: | PCG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 8.7 x 3.8 x 1.47 |
| Pitch (mm): | 0.64 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 55 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | No |
| Core Voltage (V) | 3.3 |
| Die Form | No |
| Feedback Input | No |
| Input Freq (MHz) | 12.5 - 12.5, 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 7 |
| Length (mm) | 8.7 |
| MOQ | 165 |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 100 - 100, 75 - 75, 33.3333 - 33.3333, 66.6667 - 66.6667, 16.6667 - 16.6667, 83.3333 - 83.3333, 41.6667 - 41.6667, 133.333 - 133.333, 125 - 125, 25 - 25, 50 - 50, 37.5 - 37.5, 8.3333 - 8.3333, 20.8333 - 20.8333, 62.5 - 62.5, 12.5 - 12.5 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 7 |
| Package Area (mm²) | 33.1 |
| Period Jitter Typ P-P (ps) | 150 |
| Pitch (mm) | 0.64 |
| Pkg. Dimensions (mm) | 8.7 x 3.8 x 1.47 |
| Pkg. Type | QSOP |
| Prog. Clock | No |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1.47 |
| Width (mm) | 3.8 |
| Xtal Freq (KHz) | 12.5 - 12.5 |
| Xtal Inputs (#) | 1 |
| 已发布 | No |
有关 650-27 的资源
描述
The IDT650-27 is a low cost, low-jitter, high-performance clock synthesizer for networking applications. Using analog Phase Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASIDT. The IDT650-27 outputs all have zero ppm synthesis error. The IDT650-27 is pin compatible and functionally equivalent to the IDT650-07. It is a performance upgrade and is recommended for all new 3.3 V designs. See the MK74CB214, IDT551, and IDT552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the IDT570, IDT9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.