封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | DCG8 |
| Lead Count (#): | 8 |
| Pkg. Dimensions (mm): | 4.9 x 3.9 x 1.5 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | SOIC |
| Lead Count (#) | 8 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Accepts Spread Spec Input | No |
| Core Voltage (V) | 3.3V, 5V |
| Divider Value | 2, 8 |
| Feedback Input | Yes |
| Input Freq (MHz) | 8 |
| Input Type | LVCMOS |
| Inputs (#) | 5 |
| Length (mm) | 4.9 |
| MOQ | 291 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 0.25 - 120 |
| Output Signaling | CMOS, TTL |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3V, 5V |
| Outputs (#) | 1 |
| Package Area (mm²) | 19.1 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 250 |
| Period Jitter Typ P-P (ps) | 150 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 1.5 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 97 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1.5 |
| Width (mm) | 3.9 |
| 已发布 | No |
有关 663 的资源
描述
The IDT663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the IDT674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the configuration of other PLL circuits. For example, the IDT663 phase detector can be used to control a VCXO circuit such as the MK3754. For applications requiring Power Down or Output Enable features, please refer to the IDT673-01.