特性
- High-performance system speed - 150MHz (3.8ns Clock-to-Data access)
- ZBT feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (Read/Write) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 3.3V power supply (±5%)
- 3.3V I/O Supply (VDDQ)
- Power down controlled by ZZ input
- Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages
描述
The 71V65603 3.3V CMOS SRAM, organized as 256K X 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65603 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
产品参数
| 属性 | 值 |
|---|---|
| Density (Kb) | 9216 |
| Bus Width (bits) | 36 |
| Core Voltage (V) | 3.3 |
| Pkg. Code | BQG165, PKG100 |
| Organization | 256K x 36 |
| I/O Voltage (V) | 2.5 - 2.5 |
| I/O Frequency (MHz) | 100 - 100, 133 - 133, 150 - 150 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | ZBT |
| Output Type | Pipelined |