跳转到主要内容
256 x 18 SyncFIFO, 3.3V

封装信息

Lead Count (#) 64
Pkg. Code PNG64
Pitch (mm) 0.8
Pkg. Type TQFP
Pkg. Dimensions (mm) 14.0 x 14.0 x 1.4

环境和出口类别

Pb (Lead) Free Yes
Moisture Sensitivity Level (MSL) 3
ECCN (US) NLR
HTS (US) 8542320071

产品属性

Lead Count (#) 64
Pb (Lead) Free Yes
Carrier Type Reel
Moisture Sensitivity Level (MSL) 3
Price (USD) | 1ku 19.40481
Architecture Uni-directional
Bus Width (bits) 18
Core Voltage (V) 3.3
Density (Kb) 4
Family Name SyncFIFO
I/O Frequency (MHz) 1 - 1
I/O Type 3.3 V LVTTL
Interface Synchronous
Length (mm) 14
MOQ 750
Organization 256 x 18
Package Area (mm²) 196.0
Pb Free Category e3 Sn
Pitch (mm) 0.8
Pkg. Dimensions (mm) 14.0 x 14.0 x 1.4
Pkg. Type TQFP
Qty. per Carrier (#) 0
Qty. per Reel (#) 750
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Temp. Range -40 to 85°C
Thickness (mm) 1.4
Width (mm) 14

描述

The 72V205 is a 256 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock (WCLK) for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.