封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TQFP |
| Pkg. Code: | PN64 |
| Lead Count (#): | 64 |
| Pkg. Dimensions (mm): | 14.0 x 14.0 x 1.4 |
| Pitch (mm): | 0.8 |
环境和出口类别
| Pb (Lead) Free | No |
| Moisture Sensitivity Level (MSL) | 3 |
| ECCN (US) | |
| HTS (US) |
产品属性
| Lead Count (#) | 64 |
| Pb (Lead) Free | No |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Architecture | Uni-directional |
| Bus Width (bits) | 18 |
| Core Voltage (V) | 3.3 |
| Density (Kb) | 4 |
| Family Name | SyncFIFO |
| I/O Frequency (MHz) | 66 - 66 |
| I/O Type | 3.3 V LVTTL |
| Interface | Synchronous |
| Length (mm) | 14 |
| MOQ | 270 |
| Organization | 256 x 18 |
| Package Area (mm²) | 196 |
| Pb Free Category | e0 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 14.0 x 14.0 x 1.4 |
| Pkg. Type | TQFP |
| Qty. per Carrier (#) | 90 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1.4 |
| Width (mm) | 14 |
| 已发布 | No |
有关 72V205 的资源
描述
The 72V205 is a 256 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock (WCLK) for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.