Lead Count (#) | 32 |
Pkg. Code | PRG32 |
Pitch (mm) | 0.8 |
Pkg. Type | TQFP |
Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
Pb (Lead) Free | Yes |
Moisture Sensitivity Level (MSL) | 3 |
ECCN (US) | NLR |
HTS (US) | 8542320071 |
Lead Count (#) | 32 |
Pb (Lead) Free | Yes |
Carrier Type | Reel |
Moisture Sensitivity Level (MSL) | 3 |
Architecture | Uni-directional |
Bus Width (bits) | 9 |
Core Voltage (V) | 3.3 |
Density (Kb) | 18 |
Family Name | SyncFIFO |
I/O Frequency (MHz) | 1 - 1 |
I/O Type | 3.3 V LVTTL |
Interface | Synchronous |
Length (mm) | 7 |
MOQ | 2000 |
Organization | 2K x 9 |
Package Area (mm²) | 49.0 |
Pb Free Category | e3 Sn |
Pitch (mm) | 0.8 |
Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
Pkg. Type | TQFP |
Qty. per Carrier (#) | 0 |
Qty. per Reel (#) | 2000 |
Reel Size (in) | 13 |
Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
Tape & Reel | Yes |
Temp. Range | 0 to 70°C |
Thickness (mm) | 1.4 |
Width (mm) | 7 |
The 72V231 is a 2K x 9 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72231 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks, and interprocessor communication. The 72V231 has 9-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.