特性
- Functionally compatible with the 72V255/65/75/85 SuperSync FIFOs
- Up to 166MHz operation of the clocks
- User-selectable asynchronous read and/or write ports (BGA only)
- User-selectable input and output port bus sizing
- Pin-to-pin compatible with the higher density 72V2x3/72V21x3 devices
- 5V tolerant inputs
- Auto power-down minimizes standby power consumption
- Master Reset clears the entire FIFO
- Partial Reset clears the data, but retains programmable settings
- Easily expandable in depth and width
- JTAG port, provided for Boundary Scan function (BGA only)
- Independent Read and Write clocks
- Available in 80-pin TQFP or 100-pin BGA packages
- Industrial temperature range (–40 °C to +85 °C) is available
72V283 - Block Diagram
描述
The 72V283 64K x 9/32K x 18 SuperSync II FIFO memory has flexible x9/x18 bus-matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
产品参数
| 属性 | 值 |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 18 |
| Density (Kb) | 512 |
| Pkg. Code | PNG80 |
| Interface | Synchronous |
| I/O Type | 3.3 V LVTTL |
| I/O Frequency (MHz) | 133 - 133 |
| Organization | 32K x 18, 64K x 9 |
| Temp. Range (°C) | -40 to 85°C |
| Architecture | Uni-directional |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 14.0 x 14.0 x 1.4 | 80 | 0.65 |
