特性
- A and C speeds
- High-speed, low-power CMOS
- Typical tSK(o) (Output Skew) 250ps
- Low input and output leakage ?1 uA (max.)
- VCC = 5V ±10%
- High drive outputs (–32mA IOH, 64mA IOL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) 1.0V at VCC = 5V, TA = 25C
- Available in 56 pin SSOP and TSSOP packages
74FCT16543T - Block Diagram
描述
The 74FCT16543T 16-bit high-speed, low-power latched transceiver is organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. The 74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The 74FCT16543T operates at -40C to +85C
