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瑞萨电子 (Renesas Electronics Corporation) - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community

特性

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

描述

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
74SSTUBF32868ABKGObsoleteN/AOut of StockCABGA176#CYesTray
74SSTUBF32868ABKG8ObsoleteN/AOut of StockCABGA176#CYesReel