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FemtoClock™ Dual VCXO Video PLL

封装信息

CAD 模型: View CAD Model
Pkg. Type: VFQFPN
Pkg. Code: NLG32
Lead Count (#): 32
Pkg. Dimensions (mm): 5.0 x 5.0 x 0.9
Pitch (mm): 0.5

环境和出口类别

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 32
Carrier Type Tray
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 0
Qty. per Carrier (#) 490
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Abs. Pull Range Min. (± PPM) 50
Core Voltage (V) 3.3
Feedback Input No
Input Freq (MHz) 0.015609 - 0.0675
Input Type LVCMOS
Inputs (#) 2
Length (mm) 5
MOQ 490
Output Banks (#) 1
Output Freq Range (MHz) 26 - 28, 31 - 175
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 1
Package Area (mm²) 25
Phase Jitter Typ RMS (ps) 1.01
Pitch (mm) 0.5
Pkg. Dimensions (mm) 5.0 x 5.0 x 0.9
Pkg. Type VFQFPN
Prog. Clock No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 0.9
Width (mm) 5
已发布 No

描述

The 810001-22 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion. The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency video output clock. Preset multiplication ratios are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94Hz base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics.