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瑞萨电子 (Renesas Electronics Corporation)

瑞萨电子的时序产品组合已被 SiTime 收购。

数据手册、文档以及样品订购仍将通过 Renesas.com 官网提供,直至 2026 年底。如需新设计、采购、技术支持以及产品咨询,请访问 SiTime.com 官网或发送电子邮件至 [email protected]。预计于 2026 年底前全面过渡至 SiTime。

特性

  • Fourth Generation FemtoClock NG technology
  • Two LVPECL output pairs
  • Each output supports independent frequency selection at 19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
  • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL
  • Accepts input frequencies from 8kHz to 156.25MHz including 8kHz,19.44MHz, 25MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz and 156.25MHz
  • Crystal interface designed for a 27MHz, 10pF parallel resonant crystal
  • Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal
  • Customized settings for jitter attenuation and reference tracking using an external loop filter connection
  • FemtoClock NG frequency multiplier provides low jitter, high-frequency output
  • Absolute pull range: ±50ppm
  • Power supply noise rejection (PSNR): -95dB (typical)
  • FemtoClock NG VCXO frequency: 2488.32MHz
  • RMS phase jitter @ 155.52MHz, using a 27MHz crystal (12kHz '- 20MHz): 0.674ps (typical)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

描述

The 813N322I-02 device uses Renesas' fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 813N322I-02 is a PLL-based synchronous multiplier that is optimized for Ethernet to SONET/PDH clock jitter attenuation and frequency translation. The 813N322I-02 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provides the low jitter, high-frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.

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