封装信息
| Lead Count (#) | 72 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Code | NLG72 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Lead Count (#) | 72 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Advanced Features | Full SETS (ITU-T G.8264), Hitless Reference Switching, Fractional-N Input Dividers, External Sync Input, External Feedback, DCO with Physical Layer Frequency Support, LOS Inputs, DCO, IEEE 1588 Protocol Stack, IEEE 1588 Clock Recovery Servo |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Price (USD) | 1ku | 51.3253 |
| Application | System Synchronizer, IEEE 1588 Synthesizer |
| Channels (#) | 3 |
| Clock Support | G.813, G.8262, GR-1244-CORE, GR-253-CORE, G.8273.2 |
| Core Voltage (V) | 1.8 |
| Diff. Inputs | 4 |
| Diff. Outputs | 2 |
| Input Freq (MHz) | 0.000001 - 650 |
| Input Freq Range Type | 1PPS (1 Hz), TDM, DS1, E1, SONET/SDH, Ethernet, OTN, Sync Pulse |
| Input Type | LVCMOS, LVPECL, LVDS |
| Inputs (#) | 6 |
| Length (mm) | 10 |
| MOQ | 168 |
| Output Freq Range (MHz) | 0.000001 - 650 |
| Output Freq Range Type | 1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X, STM-16/OC-48 |
| Output Type | LVCMOS, LVPECL, LVDS |
| Outputs (#) | 9 |
| Package Area (mm²) | 100.0 |
| Phase Jitter Typ RMS (ps) | 0.560 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
描述
The 82P33913 synchronization system for IEEE 1588 is comprised of software and hardware designed to meet the needs of IEEE 1588 slave clock and master clock applications. The system includes a clock recovery servo software (Servo) that runs on an external processor and Synchronization Management Unit (SMU) hardware. The Servo recovers accurate and stable electrical synchronization signals from packet-based references generated by IEEE 1588 masters. The Servo is capable of filtering the effects of Packet Delay Variation (PDV) often present in IEEE 1588 unaware networks.
The SMU hardware provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The 82P33913 supports up to three independent timing paths that control IEEE 1588 clock synthesis, SyncE clock generation, and general-purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet-based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH, and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
For more information, please contact your local Renesas sales representative.