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瑞萨电子 (Renesas Electronics Corporation)
Low Skew,1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PRG32
Lead Count (#):32
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.8

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)32
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Additive Phase Jitter Typ RMS (fs)30
Additive Phase Jitter Typ RMS (ps)0.03
Core Voltage (V)3.3V, 2.5V
Diff. Input Signaling3.3, 2.5
FunctionBuffer, Multiplexer
Input Freq (MHz)250
Input TypeLVCMOS, SSTL, CML, LVPECL
Inputs (#)2
Length (mm)7
MOQ2000
Multiply/Divide Value1
Output Banks (#)1
Output Freq Range (MHz)250
Output SignalingLVCMOS
Output Skew (ps)200
Output TypeLVCMOS
Output Voltage (V)3.3V, 2.5V
Outputs (#)18
Package Area (mm²)49
Pitch (mm)0.8
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Pkg. TypeTQFP
Product CategoryClock Buffers & Drivers, Clock Multiplexers
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)3.3 - 3.3
Tape & ReelYes
Thickness (mm)1.4
Width (mm)7
已发布No

描述

The 83940D is a low skew, 1-to-18 LVPECL-to- LVCMOS/LVTTL Fanout Buffer. The 83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940D is characterized at full 3.3V and 2.5V or mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well defined performance and repeatability.