封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 32 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| 100M Non-SSC Outputs | 4 |
| 100M SSC Outputs | 0 |
| 25M Outputs | 0 |
| Advanced Features | Programmable Clock, 100M output(s), 125M output(s), 156.25M output(s), 250M output(s) |
| App Jitter Compliance | XAUI, RXAUI |
| Chipset Manufacturer | Cavium |
| Clock Spec. | Cavium: Period Jitter < 44 ps |
| Core Voltage (V) | 2.5V, 3.3V |
| Diff. Termination Resistors | 10 |
| Feedback Input | No |
| Function | Generator |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 2 |
| Lead Compliant | No |
| Length (mm) | 5 |
| MOQ | 490 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 100 - 100, 125 - 125, 156.25 - 156.25, 250 - 250 |
| Output Skew (ps) | 2700 |
| Output Type | LVDS, HCSL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 4 |
| PCI 33.33M Outputs (#) | 0 |
| Package Area (mm²) | 25 |
| Phase Jitter Typ RMS (ps) | 0.27 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 834 |
| Product Category | FemtoClock, Ultra-Low Jitter Clocks (<300 fs RMS), PCI Express Clocks, Processor Clock Generators |
| Prog. Clock | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 2.5 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (MHz) | 25 - 25 |
| 已发布 | No |
有关 841N254I 的资源
描述
The 841N254I is a 4-output clock synthesizer designed for S-RIO 1.3 and 2.0 reference clock applications. The device generates four copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz clock signal with excellent phase jitter performance. The four outputs are organized in two banks of two LVDS and two HCSL outputs. The device uses Renesas' fourth generation FemtoClock™ NG technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. The synthesized clock frequency and the phase-noise performance are optimized for driving RIO 1.3 and 2.0 SerDes reference clocks. The device supports 3.3V and 2.5V voltage supplies and is packaged in a small 32-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.