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Low Skew,1-to-6,Crystal/LVCMOS/Differential-to-3.3V,2.5V LVPECL Fanout Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG24
Lead Count (#):24
Pkg. Dimensions (mm):7.8 x 4.4 x 1.0
Pitch (mm):0.65

环境和出口类别

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)24
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)62
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Additive Phase Jitter Typ RMS (fs)190
Additive Phase Jitter Typ RMS (ps)0.19
Core Voltage (V)2.5V, 3.3V
FunctionBuffer, Multiplexer
Input Freq (MHz)700
Input TypeCrystal, HCSL, LVDS, HSTL, LVPECL, SSTL
Inputs (#)3
Length (mm)7.8
MOQ62
Output Banks (#)1
Output Freq Range (MHz)700
Output Skew (ps)55
Output TypeLVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)6
Package Area (mm²)34.3
Pitch (mm)0.65
Pkg. Dimensions (mm)7.8 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers, Clock Multiplexers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

描述

The 8536-01 is a low skew, high performance 1-to-6 Selectable Crystal, Single-Ended, or Differential Input-to-3.3V, 2.5V LVPECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8536-01 has selectable crystal, single ended or differential clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVPECL levels. The CLK1, nCLK1 pair can accept most standard differential input levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8536-01 ideal for those applications demanding well defined performance and repeatability.