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瑞萨电子 (Renesas Electronics Corporation)
Low Skew, 1-to-15 LVCMOS/LVTTL Clock Generator

封装信息

CAD 模型:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PPG52
Lead Count (#):52
Pkg. Dimensions (mm):10.0 x 10.0 x 1.4
Pitch (mm):0.65

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)52
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFeedback Input
C-C Jitter Typ P-P (ps)100
Core Voltage (V)3.3
Feedback InputYes
Input TypeLVCMOS
Inputs (#)2
Length (mm)10
MOQ500
Output Banks (#)3
Output Freq Range (MHz)8.33 - 125
Output Skew (ps)350
Output TypeLVCMOS
Output Voltage (V)3.3
Outputs (#)14
Package Area (mm²)100
Pitch (mm)0.65
Pkg. Dimensions (mm)10.0 x 10.0 x 1.4
Pkg. TypeTQFP
Product CategoryZero Delay Buffers
Prog. ClockNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1.4
Width (mm)10
已发布No

描述

The 87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources. Guaranteed low jitter and output skew characteristics make the 87974I ideal for those applications demanding well defined performance and repeatability.