特性
- 32 PCIe Gen1 Lanes, 16 Switch Ports
- Non-blocking switch architecture optimized for High Performance System Interconnect
- Partionable switch architecture for true multi-root support
- Internal buffering and flow control credits optimized for maximum bandwidth and large payloads
- Low latency, Low power
描述
Provides 34 PCIe lanes and 16 ports of high-performance, deterministic system interconnect switching. All ports receive full line rate, non-blocking throughput for multiple traffic flows regardless of switch loading.