封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CLCC |
| Pkg. Code: | CD10 |
| Lead Count (#): | 10 |
| Pkg. Dimensions (mm): | 7.0 x 5.0 x 1.5 |
| Pitch (mm): | 2.54 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 10 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 364 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e4 Au |
| Temp. Range (°C) | -40 to 85°C |
| Abs. Pull Range Min. (± PPM) | 100 |
| C-C Jitter Max P-P (ps) | 20 |
| Family Name | FemtoClock NG |
| Feedback Input | No |
| Freq. Accuracy Init. (± PPM) | 10 |
| Freq. Accuracy Temp. (± PPM) | 50 |
| Freq. Stability Total (± PPM) | 63 |
| Function | XO |
| Length (mm) | 7 |
| MOQ | 364 |
| Output Freq Range (MHz) | 15.476 - 866.67, 975 - 1300 |
| Output Type | LVPECL |
| Outputs (#) | 1 |
| Package Area (mm²) | 35 |
| Period Jitter Max P-P (ps) | 4 |
| Period Jitter Typ P-P (ps) | 2.85 |
| Phase Jitter Max RMS (fs) | 990 |
| Phase Jitter Max RMS (ps) | 0.99 |
| Phase Jitter Typ RMS (fs) | 475 |
| Phase Jitter Typ RMS (ps) | 0.475 |
| Pitch (mm) | 2.54 |
| Pkg. Dimensions (mm) | 7.0 x 5.0 x 1.5 |
| Pkg. Type | CLCC |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1.5 |
| Width (mm) | 5 |
| 已发布 | No |
有关 8N3Q001 的资源
描述
The 8N3Q001 is a Quad-Frequency Programmable Clock Oscillator with very flexible frequency programming capabilities. The device uses IDT's fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x 7mm x 1.55mm package. Besides the four default power-up frequencies set by the FSEL0 and FSEL1 pins, the 8N3Q001 can be programmed via the I2C interface to output clock frequencies between 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to a very high degree of precision with a frequency step size of 435.9Hz ÷ N (N is the PLL output divider). Since the FSEL0 and FSEL1 pins are mapped to 4 independent PLL M and N divider registers (P, MINT, MFRAC and N), reprogramming those registers to other frequencies under control of FSEL0 and FSEL1 is supported. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.