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瑞萨电子 (Renesas Electronics Corporation)
Low Skew,÷2,÷4,÷8 Differential-to-LVPECL Clock Divider

封装信息

CAD 模型:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG16
Lead Count (#):16
Pkg. Dimensions (mm):5.0 x 4.4 x 1.0
Pitch (mm):0.65

环境和出口类别

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)16
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Carrier (#)0
Package Area (mm²)22
Pitch (mm)0.65
Pkg. Dimensions (mm)5.0 x 4.4 x 1.0
Qty. per Reel (#)2500
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Adjustable PhaseNo
Channels (#)1
Core Voltage (V)2.5V, 3.3V
Divider Value2, 4, 8
FunctionDivider
Input Freq (MHz)3200
Input TypeCML, LVDS, LVPECL, SSTL
Inputs (#)1
Length (mm)5
MOQ2500
Output Banks (#)3
Output Freq Range (MHz)3200, 1600, 800
Output Skew (ps)50
Output TypeLVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)3
Pkg. TypeTSSOP
Product CategoryClock Dividers, RF Buffers
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5, 3.3 - 3.3
Tape & ReelYes
Thickness (mm)1
Width (mm)4.4

描述

The 8S73034I is a high-speed, differential-to- LVPECL clock divider designed for high-performance telecommunication, computing and networking applications. High clock frequency capability and the differential design make the 8S73034I an ideal choice for performance clock distribution networks. The device frequency-divides the input clock by ÷2, ÷4 and ÷8. Each frequency-divided clock signal is output at a separate LVPECL output. The differential input pair can be driven by LVPECL, LVDS, CML and SSTL signals. Single-ended input signals are supported by using the integrated bias voltage generator (VBB). The 8S73034I is optimized for 3.3V and 2.5V power supply voltages and the temperature range of -40 to +85°C. The device is available in space-saving 16-lead TSSOP and SOIC packages.